Cypress Semiconductor /psoc63 /SCB0 /UART_FLOW_CTRL

Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to ‘0’, flow control is effectively disabled (may be useful for debug purposes).

Polarity of the RTS output signal: ‘0’: RTS is active low; ‘1’: RTS is active high;

During SCB reset (Hibernate system power mode), RTS output signal is ‘1’. This represents an inactive state assuming an active low polarity.

Polarity of the CTS input signal ‘0’: CTS is active low ; ‘1’: CTS is active high;

Enable use of CTS input signal by the UART transmitter: ‘0’: Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. ‘1’: Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register.

If UART_CTRL.LOOPBACK is ‘1’, the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY).